? semiconductor components industries, llc, 2007 march, 2007 ? rev. 1 1 publication order number: 74hct157/d 74hct157 quad 2?input data selectors / multiplexers high ? performance silicon ? gate cmos the 74hct157 is identical in pinout to the ls157. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device routes 2 nibbles (a or b) to a single port (y) as determined by the select input. the data is presented at the outputs in noninverted form. a high level on the output enable input sets all four y outputs to a low level. features ? output drive capability: 10 lsttl loads ? ttl/nmos ? compatible input levels ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? esd performance: hbm 2000 v; machine model 200 v ? chip complexity: 82 fets or 20.5 equivalent gates ? these are pb ? free devices http://onsemi.com marking diagrams soic ? 16 d suffix case 751b tssop ? 16 dt suffix case 948f 1 16 1 16 1 16 hct157g awlyww hct 157 alyw 1 16 74hct157 = device code a = assembly location l, wl = wafer lot y = year w, ww = work week g or = pb ? free package see detailed ordering and shipping information in the package dimensions sect ion on page 2 of this data sheet. ordering information (note: microdot may be in either location)
74hct157 http://onsemi.com 2 2 5 11 14 3 6 10 13 4 7 9 12 1 15 a0 a1 a2 a3 b0 b1 b2 b3 y0 y1 y2 y3 select output enable data outputs nibble a inputs nibble b inputs pin 16 = v cc pin 8 = gnd function table inputs output outputs enable select y0 ? y3 x = don?t care a0 ? a3, b0 ? b3 = the levels of the respective data ? word inputs. h l l x l h l a0 ? a3 b0 ? b3 figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 select y0 b0 a0 y1 b1 a1 gnd y3 b3 a3 output enable v cc b2 a2 y2 figure 2. logic diagram ordering information device package shipping ? 74hct157dr2g soic ? 16 (pb ? free) 2500 units / reel 74HCT157DTR2G tssop ? 16* 2500 units / reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
74hct157 http://onsemi.com 3 ??????????????????????? ??????????????????????? v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, soic package? tssop package? 500 450 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds (soic or tssop package) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ?derating ? soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d). recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns dc electrical characteristics (voltages referenced to gnd) v cc (v) guaranteed limit symbol parameter condition ? 55 to 25 c 85 c 125 c unit v ih minimum high ? level input voltage v out = 0.1v |i out | 20 a 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum low ? level input voltage v out = v cc ? 0.1v |i out | 20 a 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 v v oh minimum high ? level output voltage v in = v il |i out | 20 a 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 v v in = v il |i out | 4.0ma 4.5 3.98 3.84 3.70 v ol maximum low ? level output voltage v in = v ih |i out | 20 a 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih |i out | 4.0ma 4.5 0.26 0.33 0.40 i in maximum input leakage current v in = v cc or gnd 5.5 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 5.5 4.0 40 40 a i cc additional quiescent supply current v in = 2.4v, any one input v in = v cc or gnd, other inputs i out = 0 a 5.5 ? 55 c 25 to 125 c ma 2.9 2.4 1. information on typical parametric values can be found in chapter 2 of the on semic onductor high ? speed cmos data book (dl129/d). 2. total supply current = i cc + i cc . this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
74hct157 http://onsemi.com 4 ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter v cc (v) guaranteed limit unit ? 55 to 25 c 85 c 125 c t plh , t phl maximum propagation delay, input a or b to output y (figures 1 and 4) 4.5 21 26 32 ns t plh , t phl maximum propagation delay, select to output y (figures 2 and 4) 4.5 22 28 33 ns t plh , t phl maximum propagation delay, output enable to output y (figures 3 and 4) 4.5 20 25 30 ns t tlh , t thl maximum output transition time, any output (figures 1 and 4) 4.5 15 19 22 ns c in maximum input capacitance ? 10 10 10 pf note: for propagation delays with loads other than 50 pf, and info rmation on typical parametric values, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d). c pd power dissipation capacitance (per package)* typical @ 25 c, v cc = 5.0 v pf 33 * used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d).
74hct157 http://onsemi.com 5 pin descriptions inputs a0, a1, a2, a3 (pins 2, 5, 11, 14) nibble a inputs. the data present on these pins is transferred to the outputs when the select input is at a low level and the output enable input is at a low level. the data is presented to the outputs in noninverted form. b0, b1, b2, b3 (pins 3, 6, 10, 13) nibble b inputs. the data present on these pins is transferred to the outputs when the select input is at a high level and the output enable input is at a low level. the data is presented to the outputs in noninverted form. outputs y0, y1, y2, y3 (pins 4, 7, 9, 12) data outputs. the selected input nibble is presented at these outputs when the output enable input is at a low level. the data present on these pins is in its noninverted form. for the output enable input at a high level, the outputs are at a low level. control inputs select (pin 1) nibble select. this input determines the data word to be transferred to the outputs. a low level on this input selects the a inputs and a high level selects the b inputs. output enable (pin 15) output enable input. a low level on this input allows the selected input data to be presented at the outputs. a high level on this input sets all outputs to a low level. switching waveforms input a or b output enable t plh t phl t r t f v cc gnd t thl t tlh 10% 50% 90% 10% 50% 90% output y *includes all probe and jig capacitance c l * test point device under test output t r t f v cc gnd output y t phl t plh 10% 50% 90% 10% 50% 90% t tlh t thl t r t f v cc gnd select output y t phl t plh t tlh t thl 10% 50% 90% 10% 50% 90% figure 3. hct157 figure 4. y versus selected, noninverted figure 5. hct157 figure 6. test circuit
74hct157 http://onsemi.com 6 expanded logic diagram 4 7 9 12 2 3 5 6 11 10 14 13 15 1 a0 b0 a1 b1 a2 b2 a3 b3 y0 y1 y2 y3 output enable select data outputs nibble outputs
74hct157 http://onsemi.com 7 package dimensions soic ? 16 case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
74hct157 http://onsemi.com 8 package dimensions tssop ? 16 case 948f ? 01 issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
74hct157 http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 74hct157/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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